The present invention generally relates to majority voting of signals, and in particular to a majority voting circuit, and also to testing and maintenance of majority voting.
Majority voting is frequently utilized in a wide variety of technical applications in many technical fields. In particular, majority voting is of great importance in fault tolerant or redundant systems. Examples of such systems are clock generating systems and data processing systems.
In general, a majority voting circuit accepts a plurality of logical input signals to generate a logical output signal that is representative of the majority vote of the input signals. In the case of three input signals, the majority vote is generally performed according to the following simple Boolean expression: (A AND B) OR (A AND C) OR (B AND C), where A, B and C represent the logical levels of the signals that are input to the majority voting circuit. If all three input signals are present, the majority voting circuit sets the majority voted output signal to a high level if a majority of the three incoming signals are at high level, otherwise the output signal will be set to a low level. In the case of a single faulty input signal, the majority voting circuit will still be able to generate a correct output signal.
However, conventional majority voting circuits have problems in effectively handling more than one faulty input signal; especially when the input signals are periodic.
U.S. Pat. No. 4,583,224 issued to Ishii et al. on Apr. 15, 1986 relates to redundancy control, and in particular to fault tolerable redundancy control using majority vote logic. There is disclosed a redundant control system in which three control signals from three equivalent signal processors are subjected to a majority vote operation in order to generate a single majority voted control signal. The majority voted control signal is used for controlling an apparatus or system such as an atomic power plant. The control signals are compared to each other, and if one of the control signals differs from the other control signals, then the different control signal is considered as abnormal and an error detection signal, corresponding to the abnormal signal, is generated. There is also provided means for generating a set signal of a predetermined level, "0" or "1". A switching device receives the control signals, the error detection signal and the set signal for forwarding the control signals that are not associated with the error detection signal to a majority logic circuit, and for forwarding the set signal to the majority logic circuit instead of the abnormal control signal. When one of the three inputs to the majority logic is fixed to have the set level of "1", the logic circuit is equivalent to an OR gate applied with the remaining inputs. On the other hand, when one of the three inputs is fixed to have the set level of "0", the logic circuit is equivalent to an AND gate applied with the remaining inputs.
Apparently, the control system in U.S. Pat. No. 4,583,224 is customized for static signals, and fail-safe control operation can be continued after the occurrence of faults in two of the three control channels only by previously determining which logical level "0" or "1" that is to be substituted for the abnormal control signal.